1. Field of the Invention
The present invention relates to a video signal clamping method and apparatus to clamp a composite video signal at a reference level. The invention is specifically directed to a video clamp circuit using MOSFETs.
2. Discussion of the Related Art
Video signals are processed in many different applications including televisions, video capture equipment, VCRs and camcorders. Over the years, the features and complexity of these machines have increased while, in some cases, their physical size has decreased. As a result, it has become necessary to provide video signal processing circuitry in smaller packages requiring less power consumption.
As shown in FIG. 1, a conventional video signal acquisition system 100 includes an input line 114 connected to one node of a capacitor 116. A second node of capacitor 116 is connected to an input element of a buffer amplifier 118. An output of the buffer amplifier 118 is connected to an input of a sample-and-hold amplifier 110. An output of the sample-and-hold amplifier 110 is operatively coupled to an input of an analog-to-digital converter (ADC) 112. An output of the ADC 112 is operatively coupled to digital signal processing (DSP) circuitry. Further, a clamping circuit 120 is operatively coupled to a reference signal V.sub.REF and also operatively coupled to the input to the buffer amplifier 118.
In operation, a video signal is provided at line 114 and then AC-coupled through the capacitor 116, of capacitance C.sub.in. The video signal is filtered by the capacitor 116 to remove the DC level from the video signal. The filtered video signal is provided as an input to the buffer amplifier 118 which conventionally amplifies the signal and provides a buffered filtered video signal as an output. The buffered video signal output of the amplifier 118 is provided to the sample-and-hold device 110. The sample-and-hold device 110 samples (and "holds") the output of the amplifier 118 and provides a sampled signal to the ADC 112. The ADC digitizes the sampled signal. The digital output word of the ADC 112 then is provided to the DSP circuitry.
By AC-coupling the video input signal to the circuitry, a user is provided with a flexible choice of input DC-level. Prior to the sampled video signal being digitized by the ADC 112, however, DC clamping should be performed to establish a signal reference level. In other words, a DC reference is provided for the filtered video signal so that the ADC 112 outputs a digital word representing zero when the level of the filtered video signal is at its lowest point; thus, maximum headroom and consistent signal processing are provided.
As shown in FIG. 2, a composite video signal 200 has a built-in synchronization interval, represented as a SYNC pulse, which interval is used (by convention) to determine a reference level. The SYNC pulse is repeated for each scan line of an image. DC clamping is provided to adjust the DC value of the bottom level of the SYNC pulse such that the output of the ADC 112 then is equal to the zero level output code. As an example, using the NTSC standard, one horizontal scan is shown as being approximately 63.5 .mu.sec in duration with the SYNC pulse having a duration of approximately 5 .mu.sec. DC clamping must occur during the SYNC pulse duration so that subsequent parts of the video signal can be accurately retrieved. As shown in FIG. 1, a clamp circuit 120 is provided to clamp the video signal at one end of the ADC range, "signal zero," thereby making maximum use of the limited headroom when low voltage power supplies are used. In an acquisition mode, the analog front-end must recover the SYNC pulse from the signal in order to activate the clamp circuit.
One conventional approach to providing a DC-clamp circuit is shown in FIG. 3A. In the open-loop circuit shown, the capacitor 116 is connected between the input line 114 and node 304 at an input of the buffer amplifier 118. A resistor 302 is connected between the node 304 and a reference voltage V.sub.REF. The reference voltage V.sub.REF is the voltage that, when applied to the ADC 112 through the buffer amplifier 118 and the sample-and-hold device 110, results in the zero level output code from the ADC 112.
As above, the capacitor 116 filters the video signal and provides a filtered video signal to the buffer amplifier 118. Since the DC component of the video signal has been removed, the resistor 302 operatively couples the filtered signal at node 304 to the reference level V.sub.REF. This circuit, however, is not optimum for a video application which requires an accurate setting of the reference level. In operation, the voltage level at node 304 is not sufficiently "pulled down" to the reference level V.sub.REF.
Rather, the average of the voltage level at node 304 is equal to V.sub.REF. As a result, when the bottom of the SYNC pulse is received as an input, zero level output code from the ADC 112 does not result.
An alternative conventional approach is shown in FIG. 3B. In the circuit shown, also an open-loop circuit, the capacitor 116 is connected in the same manner as that of FIG. 3A. Instead of resistor 302, however, a diode 306 is provided with its cathode connected to node 304 and its anode connected to the reference voltage V.sub.REF. During operation, when the SYNC pulse pulls the voltage at node 304 low, the diode 306 will turn on and will maintain the voltage level at node 304 equal to V.sub.REF -V.sub.BE (V.sub.BE being the p-n junction voltage drop across the diode which is turned on). Where A is the gain of amplifier 118, the reference level V.sub.REF would be set so that A*(V.sub.REF -V.sub.BE) is equal to the zero reference level of the ADC 112. At the end of the SYNC pulse, the positive-going edge thereof will turn the diode off and node 304 will float in response to the filtered input video signal. It is important, however, to ensure that the voltage at node 304 is less than the reference voltage V.sub.REF prior to clamping. Otherwise, proper clamping will not occur.
There are disadvantages to using the diode clamp as shown in FIG. 3B. It is known that a leakage current associated with the diode 306 will cause the DC level to droop during the horizontal scan of the video signal. In video applications, a certain, but small, amount of droop due to leakage current can be tolerated. The purpose of leakage current is to make sure that even if the voltage at node 304 is higher than V.sub.REF, the leakage current will make sure that the voltage will eventually be less than V.sub.REF. The problem is that the leakage current in the diode 306 can vary significantly from diode to diode due to processing discrepancies and such variations, which cannot be known or predicted, can affect the DC level. Further, the tolerance of the gain A of the amplifier, in combination with the leakage current of the diode 306, can also affect the accuracy of the ADC 112.
A low power DC clamping circuit which can detect a SYNC pulse from a standard composite video signal and clamp the incoming signal to a reference level during the SYNC pulse while consuming relatively little power is desired.